The IRT Saint Exupéry and the CNRS GDR SOC2 pursue their cooperation with the organization of the 2ndindustrial and academic event related to Hardware interference and temporal determinism for modern SoC.
Modern SoCs based on multicore processors become more challenging to control when supporting critical embedded applications. We propose to investigate these new hardware platforms to satisfy safety properties such as timing determinism and freedom from interference.
The objective of this day is to gather the academic and industrial communities on embedded systems design, including researchers from the hardware and software domains. In this context, we propose to explore the configuration of hardware and software architectures in modern multicore SoCs, in order to support critical embedded applications. The new standards, constraints, and challenges which system designers will have to face will be debated with a focus on timing determinism and freedom from interference characteristics of these modern hardware micro-architectures.
The day is organized around four main invited presentations and pitches/posters session based on CNRS/IRT team contributions selected by the organizing committee.
- Florian Brandner – Telecom ParisTech: «Deterministic arbitration for bus interconnexion»
- Claire Maiza – VERIMAG: «WCET and interference analysis for multicore processor»
- Robert Kaiser – Hochschule RheinMain: « Hypervisor determinism on modern SoC»
- Eric Jenn – IRT Saint Exupéry (seconded from Thales Avionics): « Parallelism and Determinism with SoC from embedded domain: The “CAPHCA” Project
- Location: B612 Building – 3 rue Tarfaya, 31405, Toulouse
- Estimated schedule: from 9:30 am to 4 pm
- Main website: https://www.irt-saintexupery.com/event/hardware-interference-temporal-determinism-modern-soc-workshop/
- Registration (free but mandatory): http://pyxqbreb.evenium.net