Calcul embarqué haute performance, Systèmes robustes fiables et sécurisés

CAPITAL WORKSHOP: sCalable And PrecIse Timing AnaLysis for multicore platforms

Friday June 14th. Toulouse and possible remote attendance

with a keynote from Liliana Cucu-Grosjean, INRIA Paris and Statinf « Statistical, stochastic or probabilistic (worst-case) execution time – what impact on the multicore time composability? »
and 4 invited speakers:
  • **Thomasz Kloda** (LAAS, Toulouse, France):
        Memory-centric scheduling for phased execution models on multi-core platforms
  • **Federico Aromolo** (Sant’Anna University, Pisa, Italy)
        Timing Analysis of Parallel and Accelerated Software with Event-Driven Delay-Induced Tasks
  • **Filippo Muzzini** (UniMORE, Modena, Italy)
        Resource Contention Analysis in GPU-Accelerated Embedded Platforms
  • **Frederic Bonamy** (Thales Avionics, Toulouse, France)
        Multicore Challenges in Avionics Applications
More details:
Free (but mandatory) registration:
Microsoft Teams link to follow remotely:

Topic of the seminar:

The design and the implementation of time-critical applications upon multi-core processors are considered. Multi-core processors have the potential to offer high computing power. Unfortunately, their extensive use of shared resources (e.g.,caches, DRAM, buses, etc.) makes the design and the implementation difficult to predict — especially in situations where hard real-time constraints must be satisfied. Recent works show that an important challenge is to design a precise and scalable timing analysis. To address this challenge the research community consider closely both sides of the system: software and hardware. The aim of this co-design approach is therefore to guarantee scalability, precision and low complexity of the solution without compromising flexible efficient use of resources. The solution must be tailored for the target application and platform. In particular by identifying the shared resources (memory, bus, cache)  and by reducing the complexity based on interference delay using, for instance, a tailored mapping/scheduling, bandwidth regulator. The solution must be also based on a good use of the hardware architecture (memory banks, cache, communication media) with techniques like physical/temporal partitioning to obtain a precise solution.


  • Thomas Carle (Université Toulouse III Paul Sabatier, IRIT, France)
  • Eric Jenn (IRT Saint-Exupéry, Toulouse, France)

Steering Commitee

  • Thomas Carle (Université Toulouse III Paul Sabatier, IRIT, France)
  • Eric Jenn (IRT Saint-Exupéry, Toulouse, France)
  • Juan M Rivas (Universidad de Cantabria, Santander, Spain)

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