MLIR: The Good, the Bad and the Ugly

Date : mardi 17 octobre 2023

Lieu : Rennes, INSA et visio (inscrivez-vous pour avoir le lien visio)

L’inscription pour assister à la journée est gratuite mais obligatoire en présentiel comme en visio. Le repas est inclus en présentiel. Le lien visio ne sera pas communiqué publiquement mais sera transmis la veille de la journée aux personnes inscrites.

Lien pour l’inscription : (c’est trop tard…)

Programme

9h30-10h : Accueil café

10h-11h : Présentation générale de MLIR

• MLIR – What and What Next, by Albert Cohen, Google

11h-12h30 : The good – some success stories

• Leveraging MLIR for GPU-accelerated stencil computing, by Jean-Michel Gorius, IRISA
• Platform-Aware FPGA System Architecture Generation based on MLIR by Christian Pilato, Politecnico di Milano

12h30-14h00 : Pause déjeuner

14h00-14h45 : The bad – some horror stories

• A way through IRs of Circt-HLS, by Simon Rokicki, IRISA

14h45-16h15 : The ugly – how to hack MLIR for research activities

• Representing Dataflow in MLIR: challenges and strategies, by Pedro Ciambra, UNICAMP / IETR
• RISC-V interpreter for specialized core simulation, by Louis Savary, IRISA

16h15 : Closing session – the next steps : « A Fistful of Dollars« 

Abstracts

MLIR – What and What Next, by Albert Cohen

Programming languages and artificial intelligence have been working hand in hand for decades. Yet, despite mutually profitable inspiration and progress, the art of compiler construction has not taken full benefit of the accelerating history of machine learning. We may actually be standing at the doorstep of a radical shift in the design of compilers. The MLIR project is one concrete illustration of how machine learning is reshaping the priorities and environment in which we design and implement compilers, with a focus on domain-specific productivity and performance. We will survey some of the research and engineering in this space. Symmetrically, compilers embrace machine learning at the core of optimization, autotuning and program synthesis algorithms; this trend also pushes for radical changes to compiler construction, pertaining to correctness, performance and agility. For example, today’s highest performance libraries and heroic accelerator programming are only made possible at the expense of a dramatic loss of programmability: are we ever going to find a way out of this portability/performance dilemma? Also, can we build a software infrastructure scalable enough to compile billions of lines of code while leveraging advanced machine-learning-based heuristics? And can we do so while enabling massive code reuse across domains, languages and hardware? We will shed some light on these questions, based on recent successes and half-successes in academia and industry, in relation to the MLIR project. We will also form an invitation to tackle these challenges in future research and software development.

Bio

Albert Cohen is a research scientist at Google. An alumnus of École Normale Supérieure de Lyon and the University of Versailles, he has been a research scientist at Inria, a visiting scholar at the University of Illinois, an invited professor at Philips Research, and a visiting scientist at Facebook Artificial Intelligence Research. Albert works on parallelizing, optimizing and machine learning compilers, and on dataflow and synchronous programming languages, with applications to high-performance computing, artificial intelligence and reactive control.

Leveraging MLIR for GPU-accelerated stencil computing, by Jean-Michel Gorius

Weather and climate models make extensive use of stencil computations to model physical phenomena. These models have grown in complexity over the past decades and make up large parts of today’s HPC workloads. With new architectures switching to heterogeneous compute nodes, climate models need to be compiled and optimized for accelerator hardware. In this presentation, we illustrate how we use the MLIR infrastructure to compile stencil code for GPU accelerators. We illustrate how we leverage the multi-level capabilities of MLIR by representing stencils in a high-level intermediate representation and subsequently lower this representation down to GPU code. We show that our toolchain outperforms the state-of-the-art when compiling the dynamical core of the European weather and climate model.

Platform-Aware FPGA System Architecture Generation based on MLIR, by Christian Pilato, Politecnico di Milano

FPGA acceleration is becoming increasingly important to meet the performance demands of modern computing, particularly in big data or machine learning applications. As such, significant effort is being put into the optimization of the hardware accelerators. However, integrating accelerators into modern FPGA platforms, with key features such as high bandwidth memory (HBM), requires manual effort from a platform expert for every new application. 

In this presentation, we will discuss our Olympus MLIR dialect and the associated Olympus-opt, a series of analysis and transformation passes on this dialect, for representing and optimizing platform aware system level FPGA architectures. By leveraging MLIR, our automation will be extensible and reusable both between many sources of input and many platform-specific back-ends.

A way through IRs of Circt-HLS, by Simon Rokicki

CIRCT (Circuit IR Compilers and Tools) is a MLIR project targeting hardware synthesis. It offers several dialects for representing circuits at different abstraction level. CIRCT can be used as a backend for emitting verilog code, or combined with other existing tools to obtain a full HLS toolchain translating C/C++ code into verilog.
In this presentation, we will explore and test several of these toolchains / IRs to measure how promising they are, what works and what does not.

RISC-V interpreter for specialized core simulation, by Louis Savary

Part of our research studies involved the utilization of DBT-based VLIW core in a big.LITTLE like system. The idea is to use the VLIW to increase performance while maintaining the energy efficiency. In this work, simulating the system (dynamic translation + execution on the VLIW) is critical, and we want a simulator which is both efficient (fast) and easy to improve (can easily add new dynamic code optimization in the DBT process). The objective of this project was to develop a processor simulator based on a dialect representing RISC-V assembly, and on the MLIR JIT engine to modify/optimize/recompile the application dynamically.

Representing Dataflow in MLIR: challenges and strategies, by Pedro Ciambra

MLIR is a powerful and flexible framework for the representation of abstractions. In this talk, we’ll go over the process of coming up with a dialect for Dataflow models of computation, making use of the functionality that MLIR affords while dealing with its limitations. We then demonstrate a use case where we use both dataflow and low-level kernel IR to co-optimize an application, achieving gains in performance and memory usage in a video processing application.

Vous trouverez les enregistrements de toutes les présentations de la journée sur le lien suivant :
https://youtube.com/playlist?list=PLmGjWuyn2GtTF9HvclZ2pW_RDdIBwBqx-&si=c0M94BUKiRIJIQDb

Le compte-rendu est disponible ici :

Organisation :

• Steven Derrien, Irisa
• David Novo, LIRMM
• Mickaël Dardaillon, IETR
• Simon Rokicki, Irisa
• Kevin Martin, Lab-STICC