L’IRT Saint Exupéry et le GDR SOC2, rejoints cette année par l’IRT Nanoelec et le GDR Sécurité Informatique, poursuivent leur coopération avec l’organisation de leur 4ème journée thématique réunissant industriels et académiques autour du thème des systèmes embarqués critiques.

Depuis quelques années, les concepteurs de systèmes embarqués critiques doivent adapter leurs stratégies relatives à la sûreté et la résilience afin de renforcer les mesures de protection et d’isolation face aux cyber-attaques potentielles ou aux usages malveillants rendus possibles par l’exposition d’interfaces publiques. Dans ce contexte, nous proposons d’axer les présentations et la discussion sur la sécurité et son impact sur la conception de systèmes sûrs.

En raison de la situation sanitaire, la journée est remaniée dans une version en ligne. Les présentations vidéos seront mises en ligne avant l’événement et un espace de discussion asynchrone sera mis en place pour permettre un premier échange entre orat(rices)eurs et participant(e)s. Le jour de l’événement, une session en direct sur le web sera mise en place pendant laquelle un court résumé de chaque présentation sera proposé, suivi d’une séance de questions/réponses et d’une session de synthèse.

Pour participer à la journée, l’inscription est gratuite mais obligatoire via le lien suivant : https://site.evenium.net/whhcb9mm

Calendrier prévisionnel

  • Ouverture des inscriptions : 19 octobre 2020
  • Mise en ligne des vidéos : 19 octobre 2020
  • Phase de discussion en ligne : du 19 octobre au 9 novembre 2020
  • Session en direct : 12 novembre 2020 de 10h à 12h

Programme

Les résumés des présentations sont disponibles ci-dessous

  • WonderICS – Hardware-in-the-loop platform for cybersecurity, par Pierre-Henri Thévenon (IRT Nanoelec et CEA-LETI) et Maxime Puys (CEA-LETI)
  • Cybersecurity for safety & Explicable AI: a challenge for aeronautic industry innovation, par Nathalie Feyt (Thalès Avionics)
  • Intrusion detection in critical embedded systems, par Vincent Nicomette (LAAS-CNRS)
  • Instrumentation of hardware processors for security, par Vincent Migliore (LAAS-CNRS) et Benoît Morgan (IRIT)
  • Code analysis for security, par Sébastien Bardin (CEA-LIST)
  • Safety and security of embedded systems: simulation of faults, similarities and differences, par Vincent Beroule (LCIS)

Comité d’organisation :

  • Lilian Bossuet – Laboratoire Hubert Curien, Université de Saint-Étienne
  • Philippe Cuenot – IRT Saint Exupéry (détaché de Continental Automotive)
  • Sébastien Faucou – LS2N, Université de Nantes
  • Abdoulaye Gamatié – LIRMM, Université de Montpellier, CNRS
  • Assia Tria – IRT Nanoelec et CEA-LETI

Résumés des présentations

WonderICS – Hardware-in-the-loop platform for cybersecurity

par Pierre-Henri Thévenon (IRT Nanoelec et CEA-LETI)

The main topic of this presentation is the description of a hardware-software co-simulation environment to alert the public to the danger of the cybersecurity of industrial control systems and to experiment innovative security solutions. This platform integrates simulators to emulate physical process for different use cases such as hazardous gases management or hydroelectric power plant. A set of tools can be used to attack the industrial control systems in different ways (phishing mails, corrupted usb key, hardware trojan …). This presentation will describe all the solutions used to create this platform and give some perspectives about the future work on this subject.

Cybersecurity for safety & Explicable AI: a challenge for aeronautic industry innovation

par Nathalie Feyt (Thalès Avionics)

This talk provides an overview of Thales research in cyber security for aeronautic systems. In such critical, real time and safety related equipment, traditional information security solutions need far more than integration or adaptation, they need full remastering. We have worked on various projects with Universities & Engineering Schools & start-up to manage it those challenges. Through three uses cases on embedded SIEM, Drones cybersecurity and intrusion detection on IMA- integrated modular avionics, we will show various type of approaches including IA, encompassing both technics and organizations as a factor of success. Finally, we will give perspectives on future research needs in our avionics domain.

Intrusion detection in critical embedded systems

par Vincent Nicomette (LAAS-CNRS)

This talk gives an overview of two research works carried out at LAAS-CNRS, jointly with Renault and Thales Avionics, and focusing on the design of intrusion detection systems fit respectively for vehicular networks and avionics platforms. The first research work proposes the design of an Intrusion Detection System (IDS) fit for these vehicular networks. Leveraging the high predictability of embedded automotive systems, the approach uses language theory to elaborate a set of attack signatures derived from behavioral models of the automotive ECUs in order to detect a malicious sequence of messages through the internal network. The second research work presents an approach to integrate an intrusion detection system inside an avionics computer, compliant with the Integrated Modular Avionics (IMA) development process. This approach builds a model of the normal behavior of an avionics application during the integration phase, based on the static and deterministic characteristics of this application. This normal behavior model is embedded inside the aircraft during the operational phase, and any behavioral deviation from this model is considered as an anomaly and raises an alert. This research work also investigates a post-analysis of the anomalies in order to provide a first level of on-board diagnosis.

Instrumentation of hardware processors for security

par Vincent Migliore (LAAS-CNRS) et Benoît Morgan (IRIT)

Recent attacks such as Spectre and Meltdown targets some micro-architectural elements of processors to access logically isolated information. This kind of attacks is especially critical because hardware is not easily patchable unlike software. Recent studies proposed to design new reconfigurable modules, integrated into processors, to observe micro-architectural events and raise alerts when an attack occurs. In this presentation, we will briefly describe existing strategies, their limitations and the remaining challenges.

Code analysis for security

par Sébastien Bardin (CEA-LIST)

While digital security concerns increase, we face both an urging demand for more and more code-level security analysis and a shortage of security experts. Hence the need for techniques and tools able to automate part of these code-level security analyses. As source-level program analysis and formal methods for safety-critical applications have made tremendous progress in the past decade, it is extremely tempting to adapt them from safety to security. In this talk, we will first present some of the new challenges faced by formal methods and program analysis in the context of code-level security. For example, security-oriented code analysis is better performed at the binary level and the attacker must be taken into account. Second, we will discuss some early results and achievements. Especially, we will show how techniques such as symbolic execution and SMT constraint solving can be used in a number of code-level security scenarios.

Safety and security of embedded systems: simulation of faults, similarities and differences

par Vincent Beroule (LCIS)

Fault simulation is a proven technique for evaluating both the robustness of critical circuits to disturbances and secure circuits to fault attacks. However, this technique for complex circuits or systems is facing an explosion in the number of faults to be injected. Increasing the level of abstraction of the circuit descriptions and fault models used can reduce simulation times but can drive to inaccurate evaluations. The tools and approaches used in safety and security in this context have strong similarities, but the metrics and methods for assessment differ on some points. In this presentation, we will try to illustrate these similarities and differences. We will show how cross layer approaches can improve assessment results both in terms of accuracy and speed. To do so, we will compare the work and results of two projects in progress, one in safety with an application for aeronautics (Safe-Air: Safety of Critical Systems Applied to Aeronautics), and one in security for the vulnerability analysis of embedded codes (CLAM: Cross-Layer Fault Analysis for Microprocessor Architectures).