Emerging Interconnect Technologies in ManyCore architectures
Paris, cité internationale – Collège d’Espagne

“Emerging Interconnect Technologies in ManyCore architectures”

Jointly organized by “Emerging technologies” and “High performance embedded computing” axes


Date:     27 November 2017


Place:    Paris, cité internationale – Collège d’Espagne

Collège d’Espagne.

Cité internationale universitaire de Paris

7E, bd Jourdan – 75014 Paris


The colloquium will provide technical information about emerging interconnect technologies, with the focus on Carbon Nanotubes (CNT), 3D integration and optical interconnects in silicon photonics. A broad overview of all the major aspects of BEOL interconnects will be offered, ranging from the innovative growth/deposition techniques of local and global lines to the novel measurement and simulation methodologies developed to characterize interconnect performances and novel architecture paradigms for energy efficiency. International scientific experts from both academia and research centers will give the presentations and will enrich the global perspective of the colloquium.


Target Audience

The target audience is students, researchers, engineers and entrepreneurs who have an interest or work in the areas related to advanced and future interconnects for integrated circuits. Since interconnects delay is a major limitation to circuits performance, anyone interested in advanced CMOS technologies and on new Network-on-Chip technologies will benefit from the topics addressed by the experts. Researchers working in the field of emerging technologies even if not for with direct application in interconnects technology, will also find cross-disciplinary interest in this workshop. Finally, CMOS circuit designers will be able to gather useful information on modeling; design and optimization opportunities offered by novel interconnect technologies.


Registration Fee

Participation is free but registration is mandatory. Please sign up at the following link:


Deadline for registration is November 17th.


Scientific Program

9:30 – 9:45    Arrival and coffee 

9:45 – 10:00  Welcome note from organizers

10:00 – 10:45 Transforming Nanodevices into Nanosystems: The N3XT 1,000X 

By Prof. Subhasish Mitra, Stanford University, USA

The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent advances across the computing stack: (a) new logic devices using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency; (b) high-density non-volatile resistive and magnetic memories; (c) ultra-dense (e.g., monolithic) three-dimensional integration of logic and memory with fine-grained connectivity; (d) new IC architectures for computation immersed in memory; and, (e) new materials technologies and their integration for efficient heat removal. Compared to conventional approaches, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude. Such massive benefits enable new frontiers of applications for a wide range of computing systems, from embedded systems to the cloud.


10:45 – 11: 30 Carbon nanotube interconnects: current status and prospects

By Dr. Raphael Ramos, CEA-LITEN, FR 

The use of carbon nanotubes (CNT) as nanoscale electrical conductors to replace copper in microelectronics interconnects is much desired owing to the higher current-carrying capacity of CNTs compared to copper. Both vertical and horizontal CNT interconnects have been demonstrated, however the electrical performances of the integrated materials are generally far from theoretical and lab-scale values. In this talk we will detail the current status on CNT interconnects and discuss the limitations. The various solutions being investigated to address these issues will also be introduced.


11:30 – 12:15 Recent advances in silicon Photonics for optical interconnects applications

By Prof. Laurent Vivien, Centre de Nanosciences et Nanotechnologies (C2N) – CNRS UMR 9001 – Université Paris Sud – Universite Paris Saclay – 91430 Orsay Cedex France

Silicon is the mainstream material in the electronic industry and it is rapidly expanding its dominance into the field of photonics. Indeed, silicon photonics has been the subject of intense research activities in both industry and academia as a compelling technology paving the way for next generation of energy-efficient high-speed computing, information processing and on-chip communications systems. The trend is to use optics in intimate proximity to the electronic circuit, which implies a high level of optoelectronic integration. Over the last decade, the field of silicon photonics has advanced at a remarkable pace. Most applicative sectors have now included silicon photonics in their roadmaps as a key technology to be deployed over short, medium or long-term horizons. This evolution towards silicon-based technologies is largely based on the vision that silicon provides a mature integration platform supported by the enormous existing CMOS manufacturing infrastructure which can be used to cost-effectively produce integrated optoelectronic circuits for a wide range of applications, including telecommunications, optical interconnects, medical screening, spectroscopy, and biological and chemical sensing…

An overview of the main achievements in silicon photonics will be presented highlighting on high speed optoelectronic devices including photodetectors and modulators and their integration in silicon platform for optical interconnects.


12:15 – 14:00  Lunch


14:00 – 14:45 WiNoCoD: A Dynamically Reconfigurable RF NoC for Many-Core

By Dr. Julien DENOULET, Laboratoire d’Informatique de Paris 6 (LIP6) – UMR 7606 – Université Pierre et Marie Curie – 75252 Paris Cedex France

The increase of the number of computing cores on the same chip causes a growth in communication needs.These needs are unevenly distributed in the circuit, and may change over time, depending on the applications running on the chip. This spatial and temporal heterogeneity is difficult to consider in conventional network-on-chip architectures.

To address these issues, the WiNoCoD architecture, developed in the ANR project of the same name, implements a dynamically reconfigurable on-chip interconnection network using radio frequency. We present the reasons for the choice of the RF compared to other new technologies of the field (optical, 3D), then we will detail the architecture of the WiNoCoD network, and the many-cores architecture hosting it. We then present the mechanism of dynamic allocation of the frequency bands within the network. We will finally do a feasibility study and an evaluation of the performances of the architecture through various simulations.


14:45 – 15: 30 Communication allocation in a ManyCore Architecture based on an Optical NoC

By Pr. Daniel CHILLET,  Institut de recherche en informatique et systèmes aléatoires (IRISA) – UMR 6074 – Université Rennes 1 – 22305 Lannion Cedex France

Multiprocessor System-on-Chip (MPSoC) are evolving towards the integration of hundreds of cores on a single chip. However, this increase in performance and the parallelization of applications induce an increase in exchanges between the computing cores, and deport some of the design difficulty on the integrated interconnection network within the chip.

While on-chip networks can address this issue, they become a bottleneck when the number of cores increases too much due to the high traffic generated, and suffer from an increase in latency and power consumption. Theses drawbacks lead to a limitation of the overall system performance. Hence, designing an efficient interconnect for such complex architectures is challenging, and there is a need to provide more efficient and scalable communication infrastructures.

Parallel to this evolution, silicon photonics has made a very significant progress, offering the possibility to integrate optical components on a silicon layer which can be « stacked » on the conventional silicon layer with the computing cores. If this solution is a really interesting opportunity to address the problem of communications within MPSoC architectures, it is however necessary to develop, in parallel with the silicon photonics technology, management strategies for this new communication medium.

This presentation will address this issue and focus on the development of a communications management strategy for an MPSOC architecture with an integrated optical network. We will show the optical components needed to « build » the integrated optical network, then we will illustrate their operation and the establishment of communications between several computing nodes, finally we will explain how this communication support can be exploited efficiently.


15:30 – 16:00   Coffee Break

16:00 – 16:45 NoC and Mixed-criticality System

By Mourad Dridi, PhD student,  LabSTICC – UMR 6285 – Université Bretagne Occidentale – 29200 Brest France

Mixed-Criticality Systems are real-time systems characterized by two or more distinct levels of criticality. In MCS, it is imperative that high-critical flows meet their deadlines while low-critical flows can tolerate some delays. Sharing resources between flows in Network-On-Chip (NoC) can lead to different unpredictable latencies and subsequently complicate the implementation of MCS in many-core architectures.

This talk will present ongoing work at Lab-STICC to enforce mixed-criticality requirements deployed over NoCs. We propose task and communication models to investigate their schedulability. Furthermore, a specific NoC router design is proposed and validated.

16:45 – 17:15 Panel Discussion

17:15 – 17:30 Wrap up/ Conclusions



Aida Todri-Sanial (LIRMM – CNRS) – aida.todri@lirmm.fr

Cédric Killian (IRISA – Université Rennes 1) – cedric.killian@irisa.fr



GDR SoC2 (http://www.gdr-soc.cnrs.fr/)

H2020 CONNECT project (www.connect-h2020.eu)

Collège d’Espagne (www.ciup.fr/college-espagnol)