Responsables de la session : Lilian Bossuet (Saint-Etienne) et Ioana Vatajelu (Grenoble)

Horaire et date de la session : Lundi 27 juin de 13h45 à 15h00

Présentations :

• Des technologies pour les systèmes de confiance par Dr. Jacques Fournier (CEA-Leti)
• Why fault coverage is not enough – Refining test for silicon life cycle management par Pr. Sybille Hellebrand (University of Paderborn, Germany)

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Des technologies pour les systèmes de confiance

L’ « EU Chips Act » publié en début d’année par la Commission Européenne reconnait que les technologies semiconducteurs sont « centrales » pour la sécurité de nos systèmes d’informations, mettant ainsi la cybersécurité au cœur des enjeux technologiques pour les composants de demain. Dans le panorama qui sera présenté dans cette présentation, nous illustrerons comment les composants matériels et logiciels de nos futurs systèmes embarqués doivent à la fois être robustifiés dès la conception contre les attaques et comment ils peuvent aussi être instrumentés pour réaliser efficacement certaines fonctions de sécurité. Nous évoquerons aussi comment la communauté française de recherche s’organise pour répondre à ces enjeux, notamment à travers les Programmes et Equipements Prioritaires de Recherche (PEPR) définis dans le cadre de la stratégie nationale d’accélération pour la cybersécurité annoncée par le Président de la République en Février 2021.

Dr Jacques Fournier est directeur de recherche et responsable de la thématique cybersécurité au CEA-Leti qu’il a rejoint en 2009. Avant cela, il a passé près de 9 ans dans l’industrie de la carte à puce. Ses sujets de recherche portent sur la sécurité des systèmes embarqués, et plus particulièrement sur les accélérateurs matériels et implémentations sécurisées de cryptographie embarquée. Il est diplômé de CentraleSupélec et a obtenu son doctorat de l’Université de Cambridge.

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Why fault coverage is not enough – Refining test for silicon life cycle management

Due to the enormous progress in technology and algorithms in recent years, integrated circuits and systems have become the core of many demanding applications. Silicon life cycle management aims at collecting and analyzing data throughout the complete life time of a system. Built-in infrastructure for on- and offline testing can be re-used for supporting maintenance and optimization tasks. In particular, in safety critical domains, periodic tests can complement concurrent checking and help to detect problems before they actually cause a failure. However, frequent tests also cause additional stress and may have a negative impact on the mission time of the system. Stress-aware tests must be developed to overcome this problem while still guaranteeing a high fault coverage. As an example, the presentation will discuss a stress-aware strategy for periodic interconnect testing in systems on chip.

Pr Sybille Hellebrand received her Diploma degree in Mathematics from the University of Regensburg, Germany, in 1986. In the same year she joined the Institute of Computer Design and Fault Tolerance at the University of Karlsruhe, Germany, where she received the Ph. D. degree in 1991. Then she was as a postdoctoral fellow at the TIMA/IMAG-Computer Architecture Group, Grenoble, France. From 1992 to 1997 she continued as an assistant professor at the University of Siegen, Germany. Before completing her Habilitation and changing to the Division of Computer Architecture at the University of Stuttgart, Germany, in 1997, she spent several months as a guest researcher with Mentor Graphics Corporation in Portland, Oregon, USA. In 1999 she moved to the University of Innsbruck in Austria as a full professor for Computer Science, and since December 2004 she holds a chair in Computer Engineering at Paderborn University, Germany.
Her main research interests include test and diagnosis of micro-electronic systems, in particular built-in test, built-in diagnosis and built-in repair for systems-on-a-chip, as well as design and synthesis of testable and reliable circuits and systems. She has published numerous papers in international conferences, workshops, and journals. Besides her activities in several program committees, she serves as an associate editor of the Journal of Electronic Testing – Theory and Applications (JETTA). From 2002 to 2009 she was a member of the editorial board of IEEE Transactions on Computer-Aided Design of Circuits and Systems.

Responsables de la session : Sébastien Faucou (Nantes) et Abdoulaye Gamatie (Montpellier)

Horaire et date de la session : Lundi 27 juin de 16h à 17h15

Présentations :

• Advanced 3D packaging solutions and system integration benefits for future computing systems par Pr. Dragomir Milojevic (Université Libre de Bruxelles)
• High Performance General Purpose Architecture and Microarchitecture par Dr. Arthur Perais (TIMA – CNRS/Université de Grenoble)

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Advanced 3D packaging solutions and system integration benefits for future computing systems

New transistor architectures and scaling boosters will enable CMOS process to reach 2 and 1nm nodes. However traditional integration approach where a single die is implemented in a package is seriously limiting the future of computing systems: memory wall bottleneck (bandwidth and energy per transferred bit), cost-effective integration of big dies, poor scaling of SRAM technology, to name a few. To overcome these limitations, 3D system integration has been proposed with various technology options to allow different die-to-die interconnect schemes. In this talk we will first propose an overview of different 3D integration technologies used for implementation of multi-die packages. We will then illustrate these technologies with existing industrial applications (HBMs, Intel Foveros, AMD V-Cache) and challenges for practical implementation (physical design and thermal aspects). Core of the talk will focus on practical 3D systems integration assuming advanced hybrid wafer-to-wafer bonding technologies that allow stacking with 3D structure pitches below 1um.  Such high-density 3D interconnects will be then used to separate lower cache memory layers from the core logic in a many-core System-on-Chip. 3D system results not only in better performance (reduced delay, better latency and power), but also in reduced system cost, since each wafer can be optimized for a given functionality (logic or memory). Finally, we will illustrate the importance of tighter system architecture & technology co-optimization, mandatory for development of future computing systems.

Pr. Dragomir Milojevic received his master’s and PhD degrees from Ecole Polytechnique of Université libre de Bruxelles (ULB), Belgium, where he holds the position of professor in digital electronics and digital systems design. In 2004 he joined IMEC where he first worked on multi-processor and Network-on-Chip architectures for low-power multimedia systems. Since 2008 he is working on system, design and technology co-optimization with advanced nodes, as well as design methodologies & tools for technology aware design of 3D integrated circuits. Dragomir Milojevic authored or co-authored more than 100 journal and conference articles and served as technical program committee member to several conferences in the field.

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High Performance General Purpose Architecture and Microarchitecture

In this talk, we will provide a broad overview of why general purpose processors are here to stay and some research directions pursued by the Computer Architecture community. We will also briefly present recent work done at TIMA to improve the performance of general purpose processors

Dr. Arthur Perais has been a Chargé de Recherche in the TIMA laboratory in Grenoble since 2020. Previously, he worked as a hardware engineer in Microsoft and Qualcomm. He obtained his PhD from the Université de Rennes in 2015.

Responsables de la session : Daniel Chillet (Rennes), Ahcène Bounceur (Brest) et Olivier Romain (Cergy)

Horaire et date de la session : Mardi 28 juin de 9h00 à 10h15

Présentations : 

• Enjeux des objets connectés vus des réseaux et des usages par Hervé Rivano (INSA / INRIA, CitiLab, Lyon)
• Energy-Efficient Tiny ML at the Edge for Next Generation of Smart Sensors, par Michele Magno (ETH Zurich)

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Enjeux des objets connectés vus des réseaux et des usages

Dans cet exposé, nous présenterons les enjeux de plusieurs cas d’usages de l’Internet des Objets, en particulier dans le  contexte des villes intelligentes. Nous regarderons trois problématiques qui animent la communauté réseau et qui peuvent avoir des répercutions dans la communauté SoC2:  les déploiement de grande densité ou à grande distance, leur impact sur les protocoles d’accès et les stratégies énergétiques, la généralisation des approches issues de l’Intelligence Artificielles et la question des calculs embarqués, les questions de géolocalisation par le réseau et ce que peut apporter l’électronique.

Pr. Hervé Rivano est Professeur des Université à l’INSA de Lyon et responsable de l’équipe INRIA/INSA Agora du CITILab. Ses thèmes de recherche sont orientés sur les villes intelligentes avec un focus particulier sur le compromis capacités/énergie pour la conception de réseaux urbains et les réseaux de capteurs sans fil denses et faible coût.

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Energy-Efficient Tiny ML at the Edge for Next Generation of Smart Sensors

Wearable, intelligent, and unobtrusive smart sensor nodes that monitor the surrounding environment and even the human body have the potential to create valuable data for a wide range of applications. To attain this vision of unobtrusiveness, smart devices have to gather and analyze data over long periods of time without the need for battery frequent recharging and replacement. On the other hand, advances in low-power electronics and tiny machine learning techniques lead to many novel IoT devices making them more and more intelligent to take autonomous and low latency decisions. On the other hand, these devices have limited computational power due to the constrain of working with minimal energy to maximize the battery lifetime, thus machine learning needs to be adapted to overcome the memory and computational limits.  To, even more, prolong the energy autonomy, energy harvesting from ambient sources is a promising solution to power these low-energy IoT devices.  This talk presents a broad overview of the combination of Tiny Machine learning, low power design, and energy harvesting, when possible,  to achieve truly unobtrusive wireless smart IoT devices. As those devices are still strongly application-specific the talk includes some examples of where that combination can be a winning solution facing real application scenarios ranging from smart biomedical patches to autonomous vehicles where the energy harvesting is not possible but the low latency and autonomy brought from the tiny ML is crucial. ,

Dr. Michele Magno is head of the Center for Project-based Learning (PBL), Department of Information Technology and Electrical Engineering, ETH Zurich

Responsables de la session : Nathalie Deltimple (Bordeaux), Antoine Frappé (Marseille) et Patricie Desgreys (Paris)

Horaire et date de la session : Mardi 28 juin de 11h à 12h15

Présentations :

• Toward 6G: From New Hardware Design to Wireless Semantic and Goal-Oriented Communication Paradigms par Dr. Didier Belot (CEA-Leti, Grenoble)
• Energy harvesting : Harvestore project, implementation and low TRL perspectives using new nanomaterials par Dr. Paolo Bondavali (Thales Research & Technology, Palaiseau, France)

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Toward 6G: From New Hardware Design to Wireless Semantic and Goal-Oriented Communication Paradigms

Several speculative visions are conjecturing on what 6G services will be able to offer at the horizon of 2030. Nevertheless, the 6G design process is at its preliminary stages. The reality today is that hardware, technologies and new materials required to effectively meet the unprecedented performance targets required for future 6G services and network operation, have not been designed, tested or even do not exist yet. Today, a solid vision on the cost-benefit trade-offs of machine learning and artificial intelligence support for 6G network and services operation optimization is missing. This includes the possible support from hardware efficiency, operation effectiveness and, the immeasurable cost due to data acquisition-transfer-processing. The contribution of this paper is three-fold. This is the first paper deriving crucial 6G key performance indicators on hardware and technology design. Second, we present a new hardware technologies design methodology conceived to enable the effective software-hardware components integration required to meet the challenging performance envisioned for future 6G networks. Third, we suggest a paradigm shift towards goal-oriented and semantic communications, in which a totally new opportunity of joint design of hardware, artificial intelligence and effective communication is offered. The proposed vision is consolidated by our recent results on hardware, technology and machine learning performance.

Dr Didier Belot, after 30 years with STMicroelectronics, has joined CEA-LETI, Grenoble, France, in 2014. He works as European Programs Coordinator in the System Division; he participates to roadmaps orientations and Programs management. He has written for the H2020 CSA NEREID program dedicated to the 2020-2030 European Roadmap, the connectivity chapter. He participates to ECS-SRIA connectivity chapter, and IRDS “Outside System Connectivity” task group. He presently co-chairs the Communication & Connectivity Experts Group of H2020 CSA CORENECT project. His research present interests are the mmW propagation through plastic; RF to Information transceiver design by Mathematics; THz communications; the III-V devices over Silicon for mmW and THz applications; and RF & mmW for Quantum computing. He was member of the French National Scientific Council for Micro and Nanotechnology field from 2012 to 2016, was member of different conferences program committees as RFIC, ESSCIRC, ISSCC, IEDM. He is member of the IEEE-MTT-9 Technology Committee, (mmW & THz Devices to System), and EuMW TPC. He is reviewer for IEEE MTT, and SSC journals, and author or co-author of about 200 publications and 70 patents.

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Energy harvesting : Harvestore project, implementation and low TRL perspectives using new nanomaterials

This contribution will deal with the description of the objectives of the HARVESTORE PRCI project and with the description of the technical challenges tackled by a multidisciplinary consortium to achieve a module composed  by an energy harvesting system, an  energy storage device, and an electronic circuit to manage the energy recovered and stored. This project will be implemented in a new one where we will target a miniaturized completely autonomous sensors for space testing applications.  At the end of the project we will also talk about the research strategy at Thales Research and Technology to identify very low TRLs topic also working on new generation of nanomaterials. In this context, a short introduction to 2D topological insulators for thermoelectrics will be performed.

Dr Paolo Bondavali is in charge of nanomaterials transverse topic at Thales Research and Technology. He has more than 20 years of experience on nanomaterials and specifically on carbon nanomaterials (graphene, CNTs). Graduated from University of Parma (Italy) in 1995 (Physics), he obtained his PhD from INSA of Lyon (EEA) in 2000 and his HdR from Paris Saclay (2011). He has published around 70 scientific papers in international peer reviewed journals and he has been invited to around 80 international conference as Keynote or invited speaker. He is the first author of 10 patents on nanomaterials and energy storage. He has published two books as single author dealing with 2D materials (Graphene and related materials, Elsevier in 2017 and Exotic properties of 2D materials, De Gruyter in 01/08/2022). He has just organized a symposium at the MRS Spring meeting 2022 on 2D topological matter. He is member of the GDR NAME (nanomaterials for energy).

Responsables de la session : Gilles Sassatelli (Montpellier) et Maxime Pelcat (Rennes)

Horaire et date de la session : Mercredi 29 juin de 9h00 à 10h15

Orateurs : 

• Imageur Intelligent 3D : challenges d’embarquer de l’IA en proche capteur par Dr. Pascal Vivet (CEA-LIST, France)

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Imageur Intelligent 3D : challenges d’embarquer de l’IA en proche capteur

Les imageurs CMOS intègrent aujourd’hui de plus en plus de fonctions en proche capteur, avec les imageurs « Back-Side Illumination » (BSI), qui utilisent des technologies d’intégration 3D, intégrant deux couches : une couche pixel et une couche traitement, ce qui permet d’intégrer des fonctions de traitement avancés, aussi bien du traitement proche pixel (correction de bruit bas niveau, etc.), mais aussi des fonctions de « Computer Vision », en utilisant des coprocesseurs de type Image Signal Processing (ISP). La prochaine révolution concerne l’intégration de fonction d’IA au sein même du capteur d’image, afin de faire du traitement IA proche capteur (reconnaissance, détection, classification, etc), avec une forte contrainte de basse consommation et de faible latence.  Ceci est envisagé avec l’utilisation de technologies 3D encore plus avancées, avec l’intégration d’une troisième couche de calcul et d’extension mémoire. De nombreux challenges se posent en terme de technologie 3D, d’architecture de calcul, d’architecture d’IA et de modèle d’exécution. La présentation donnera un aperçu d’un projet structurant autour de la construction d’un imageur 3 couches, utilisant une architecture locale & distribuée, des pistes envisagées et des challenges à traiter. Des travaux autour de l’apprentissage incrémental seront aussi présentés, comme solution algorithmique permettant de mettre en place de l’apprentissage local et frugal, sachant apprendre de nouveaux concepts sans avoir à réapprendre sur l’ensemble des bases de données initiales ; avec des perspectives d’utilisation de ce type d’algorithmes dans les imageurs.

Dr. Pascal Vivet is CEA fellow and Scientific Director of the Digital Systems and Integrated Circuits Division (DSCIN) in CEA-LIST, Grenoble, France and. He received his PhD from Grenoble Polytechnical Institute in 2001, designing an asynchronous microprocessor. After 4 years within STMicroelectronics, he joined CEA-Leti in 2003 in the digital design lab. His research interests covers wide aspects of circuit and system level design, ranging from system integration, multi-core architecture, Network-on-Chip, energy efficient design, related CAD design aspects, and in strong links with advanced technologies such as 3D integration, Non-Volatile-Memories, photonics. He was project leader on 3D circuit design and integration since 2011. He is also currently co-director of the IRT Nanoelec Smart Imager program, with the objective of developing the next generation of Imager integrating advanced AI capabilities within a 3 layer-stack 3D architecture. He participates to various TPC such as ESSCIRC, DATE, 3DIC, ISLPED, ASYNC conferences. He served as a member of the organizing committee of the 3D workshops series at DATE, and to the D43D workshops. He has authored and co-authored more than 120 papers and holds several patents in the field of digital design.

Responsables de la session : Kevin Martin (Lorient), Mickael Dardaillon (Rennes)

Horaire et date de la session : Mercredi 29/06 de 10h30 à 11h45

Présentations :

• Resource-aware Machine Learning approaches: Challenges and use cases in embedded systems par Dr. Tanja Harbaum (Karlsruhe Institute of Technology, Allemagne)
• Logicielss open-source pou le hardware par Dr. Marie-Minerve Louërat (LIP6, Paris, France)

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Resource-aware Machine Learning approaches: Challenges and use cases in embedded systems

The demands laid down microarchitectures are increasing steadily, and much of the technological innovation of recent decades has only been made possible by the progress of the semiconductor industry and the accomplished increases in integrated circuit performance. A further increase of the performance of integrated circuits is no longer self-evident. New architectures have to be designed in order to meet the increasing demands at this point. With the heterogeneity of these new architectures and the huge amount of data that now need to be processed, machine learning approaches are increasingly being used. Also for the development of new cyber-physical systems (CPS) and Internet of Things (IoT) products, AI is becoming an increasingly important factor. The performance of embedded systems can be increased enormously by integrating AI algorithms that are adapted to the embedded hardware. Through a hardware/software co-design, a fast and efficient AI execution on embedded systems can be realized.

Dr Tanja Harbaum studied computer science at the Karlsruhe Institute of Technology (KIT) with a focus on computer architectures and robotics. After graduation, she worked in high-energy physics experiments on trigger systems with extreme latency requirements, as well as researched reconfigurable microarchitectures. She completed her PhD in electrical engineering in Professor Becker’s group at KIT and since 2019 she has been a team leader at the “Institut fuer Technik der Informationsverarbeitung” (ITIV). Her research focuses on the design of novel computer architectures and artificial intelligence in embedded systems. Here, a focus is on hardware/software co-design, which allows fast and efficient AI execution on embedded systems.

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Logiciels Open-Source pour le Hardware

Nous présenterons rapidement le processus de conception d’un circuit intégré sur silicium en mettant en évidence les différents coûts et problèmes de propriété intellectuelle. Nous discuterons de certains freins (licences, NDA) qui s’opposent à la diminution de ces coûts et les conséquences pour les petites entreprises et les universités. Puis nous présenterons des projets en cours qui offrent des solutions plus libres : les logiciels de conception libres et ouverts (Electronic Design Automation Free Open Source Software, licence GPL) et le matériel libre, ou « Open Hardware ». Nous montrerons en particulier comment le placeur-router Coriolis développé au LIP6 s’inscrit dans un flot de conception libre d’un circuit libre et ouvert.

Dr Marie-Minerve Louërat joined the Centre National de la Recherche Scientifique (CNRS), France in 1986. In 1992, she moved to the Computer Science Laboratory (LIP6), University Pierre et Marie Curie (now Sorbonne Université)-CNRS, France, while teaching VLSI. Between 2013 and 2018, she was the head of the System on Chip Department at LIP6. Dr. Louërat’s research interests are mixed signal oriented, they include design automation of analog and mixed-signal circuits and systems with Free and Open Source (FOS) Electronic Design Automation (EDA) tools, A/D and D/A conversion, as well as mixed signal system security. She contributes regularly to the FOS EDA tool chain Coriolis developed at LIP6. Most of her research activities have been supported by contracts, through academic and industrial cooperative projects in the framework of the FP7, Eureka/MEDEA, Catrene and Penta, and H2020 Projects. She published papers on static timing analysis, analogue and AMS design automation, analogue-to-digital converters, AMS system modelling, and simulation. In 2019, she co-chaired the FSiC2019 Conference in March 2019, Paris, France. The new edition of FSIC will be held in Paris, July 2022.

Responsables de la session : TBD

Horaire et date de la session : Lundi 27/06 de 15h à 16h

Posters présentés :

• Nanoscale electrothermal transport in 10 nm SOI FinFETs par Houssem Rezgui, Chhandak Mukherjee, Marina Deng and Cristell Maneux. (Paper ID:261)
• Emulation matérielle de FeFET sur FPGA par Paul-Antoine Matrangolo, Cédric Marchand and David Navarro. (Paper ID:5759)
• Characterization and modeling of vertical Si nanowire transistors for 3D logic circuits par Yifan Wang, Chhandak Mukherjee, Marina Deng and Cristell Maneux. (Paper ID:6477)
• On-Line Reliability Estimation of Ring Oscillator PUF par Sergio Vinagrero Gutierrez, Ioana Vatajelu and Giorgio Di Natale. (Paper ID:885)
• Analysis of Read Port Short Defects in an 8T SRAM-based IMC Architecture par Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel and Jean-Philippe Noel. (Paper ID:1035)
• Measurement and prediction of the reliability of latest generation digital components under ageing par Justin Sobas and François Marc. (Paper ID:1072)
• Key Attack Strategies Against Black-Box DNNs par Yassine Hmamouche, Yehya Nasser, Amer Baghdadi and Marc-Oliver Pahl. (Paper ID:1073)
• Defect Analysis of a Spintronic Synapse for Spiking Neural Networks par Salah Daddinounou and Elena-Ioana Vatajelu. (Paper ID:1589)
• Architecture embarquée pour la fusion de données multi-capteurs dédiée à l’intégration d’algorithmes d’apprentissage pour l’aide au pilotage d’un foot-fauteuil électrique par Marouane Ben-Akka, Camille Diou, Camel Tanougast, Loïc Sieler and Nathan Clotagatide. (Paper ID:1898)
• AsteRISC : un coeur RISC-V flexible et configurable par Jonathan Saussereau, Camille Leroux, Jean-Baptiste Begueret and Christophe Jégo. (Paper ID:5823)
• Multi-objective optimization at the EDge for Online and real-time self-Adaptation of Autonomous vehicles par Evan Flecheau, Laurent Lemarchand and Catherine Dezan. (Paper ID:8760)
• Simulation et validation expérimentale d’une commande fréquentielle d’une source d’énergie hybride pile à combustible / batterie / supercondensateur pour un drone par Thomas Pavot, Renaud Kiefer, Tedjani Mesbahi and Edouard Laroche. (Paper ID:640)
• Real-Time QCSP Communication System Prototyping par Camille Monière, Bertrand Le Gal and Emmanuel Boutillon. (Paper ID:3227)
• LoRa RSSI Fingerprint for Indoor Localization par Dany Merhej, Samuel Garcia, Iness Ahriz and Michel Terré. (Paper ID:6151)
• Adaptation 50-ohms versus haute impedance d’une antenne RMN avec son préamplificateur par Duc-Vinh Nguyen, Lucas Werling, Guilherme Baumgarten, Norbert Dumas, Morgan Madec, Latifa Fakri-Bouchet, José Bernardo, Wilfried Uhring, Luc Hebrard and Joris Pascal. (Paper ID:863)
• Low-field electromagnetic tracking using 3D magnetometer for assisted surgery par Céline Vergne, Corentin Féry, Thomas Quirin, Hugo Nicolas, Morgan Madec, Simone Hemm and Joris Pascal. (Paper ID:1400)
• Une méthode de prédistorsion numérique d’amplificateur de puissance dans le domaine séquentiel par Maxandre Fellmann, François Rivet, Nathalie Deltimple, Eric Kerhervé, Hervé Lapuyade and Yann Deval. (Paper ID:1899)
• Dispenser integrated early detection system of nosocomial infection – The suitability of microfluidic tools par Paul Perronno, Sofia Disegna, Carmen Senin, Julie Claudinon, Norbert Dumas, Winfried Römer and Morgan Madec. (Paper ID:2153)
• A magnetic safety scanner to assess the risk of magnetic interaction between portable electronics and cardiac implantable electronic devices par Thomas Quirin, Celine Vergne, Corentin Féry, Hugo Nicolas, Morgan Madec, Luc Hébrard and Joris Pascal. (Paper ID:5042)
• Hybrid Performance Prediction Models for Fully-Connected Neural Networks on MPSoC par Quentin Dariol, Sebastien Le Nours, Sebastien Pillement, Ralf Stemmer, Domenik Helms and Kim Gröttner. (Paper ID:4761)
• Energy-Based Analog Neural Network Framework par Mohamed Watfa, Alberto Garcia-Ortiz and Gilles Sassatelli. (Paper ID:6086)
• Phase-based Oscillatory Neural Network for Associative Neuromorphic Computing par Corentin Delacour and Aida Todri-Sanial. (Paper ID:6583)
• Real-Time Human Detection in Marine Environment Using Deep Learning on Edge Devices par Mostafa Rizk, Amer Baghdadi and Jean-Philippe Diguet. (Paper ID:6647)
• Analyse sémantique de bitstream : Application à la détection d’oscillateurs en anneau pour la sécurité des FPGAs par Sylvain Takougang, Andrea Pinna and Sébastien Pillement. (Paper ID:2016)
• Plateforme d’émulation d’opérateurs non-volatiles sur FPGA par Alban Nicolas, Cédric Marchand and David Navarro. (Paper ID:4018)
• From Semiconductor to Transistor-Level: Modeling, Simulation, and Layout Rendering Tools par Joao R. R. O. Martins, Francisco Alves and Pietro M. Ferreira. (Paper ID:6958)
• Electro-thermal Dynamic Model and Experimental Validation for Lithium-ion Battery par Yasser Ghoulam, Tedjani Mesbahi, Sylvain Durand and Christophe Lallement. (Paper ID:6161)

Responsables de la session : TBD

Horaire et date de la session : Mardi 28/06 de 10h15 à 11h15

Posters présentés :

• A Nanoscale Magnetic Sensor Based on a Spin Transfer Torque Magnetic Tunnel Junction par Hugo Nicolas, Ricardo Sousa, Ariam Mora-Hernandez, Lucian Prejbeanu, Luc Hebrard, Jean-Baptiste Kammerer and Joris Pascal. (Paper ID:6624)
• NiFe2O4 Nanoferrites: a Case-Study into History of Nanotechnology par Andrea Durlo, Raffaele Pisano, Franco Ronconi and Federico Spizzo. (Paper ID:6722)
• Methodology for thermal contribution extraction of 3D Vertical Nanowire Transistors par Bixente Burucoa, Lucas Réveil, Chhandak Mukherjee, Marina Deng, Cristell Maneux, Abhishek Kumar, Aurélie Lecestre and Guilhem Larrieu. (Paper ID:8069)
• Reliability Analysis of a Spiking Neural Network Hardware Accelerator par Theofilos Spyrou, Sarah Ali Elsayed, Engin Afacan, Luis Alejandro Camuñas Mesa, Bernabe Linares-Barranco and Haralampos-G. Stratigopoulos. (Paper ID:1705)
• Anti-Piracy Security for RF Transceivers par Alan Rodrigo Diaz Rizo, Hassan Aboushady and Haralampos-G. Stratigopoulos. (Paper ID:3465)
• Correlation Electromagnetic Analysis on an FPGA Implementation of CRYSTALS-Kyber par Rafael Carrera Rodriguez, Florent Bruguier and Pascal Benoit. (Paper ID:3582)
• A Software Fault Injection Framework to Evaluate the Relevance of Emerging NVM-based ANN par Amine Ayaou, Hassen Aziza, Patrick Girard, Serge Pravossoudovitch and Arnaud Virazel. (Paper ID:4151)
• Leakage Assessment through Neural Estimation of the Mutual Information par Valence Cristiani, Maxime Lecomte and Philippe Maurine. (Paper ID:8798)
• Système embarqué de mesure capacitive pour la mesure de masse basée sur des ressorts céramiques plats hélicoïdaux par Adrien Bourennane, Camel Tanougast, Camille Diou and Marouane Ben-Akka. (Paper ID:8950)
• Solution d’implémentation hardware des équations d’apprentissage d’un réseau de neurones par Ming Jun Zhang, Samuel Garcia and Michel Terré. (Paper ID:9307)
• Design optimization of flexible analog-to-feature converter for smart sensors par Mikhail Manokhin, Paul Chollet and Patricia Desgreys. (Paper ID:9262)
• Electrical modeling of wake-up radio for false wake-up prediction in sensor networks par Ruochen Ding and William Tatinian. (Paper ID:9567)
• 1.2 nW Neuromorphic Enhanced Wake-Up Radio par Zalfa Jouni, Thomas Soupizet, Siqi Wang, Aziz Benlarbi-Delai and Pietro Maris Ferreira. (Paper ID:9841)
• A 125-163 GHz Power Amplifier in 28-nm FD-SOI CMOS with 20 dB Gain and 15 dBm Psat for D-Band Applications par Antoine Lhomel, Nathalie Deltimple, François Rivet, Yann Deval and Eric Kerhervé. (Paper ID:5639)
• Uni-Traveling Carrier Photodiode Compact Modelling Enabling Monolithic OptoElectronic Integrated Circuits Design par Djeber Guendouz, Chhandak Mukherjee, Marina Deng, Patrick Mounaix and Cristell Maneux. (Paper ID:5740)
• Measurements of Clinical MRI Gradients par Hugo Nicolas, Patrick Rotach, Guilherme Baumgarten, Nicolas Weber, Julien Oster and Joris Pascal. (Paper ID:5940)
• An instrumented cardiac ablation catheter model dedicated to magnetic navigation and tracking par Thomas Quirin, Damian Gloor, Corentin Féry, Céline Vergne, Morgan Madec, Luc Hebrard and Joris Pascal. (Paper ID:8474)
• Générateur d’impulsion programmable pour stimulation atriale chez le rat pour la recherche sur l’hypertension artérielle pulmonaire par Fanny Pan, Emilie Avignon-Meseldzija, Frédéric Perros, Delphine Mika, David Boulate and Anthony Kolar. (Paper ID:9225)
• Chaîne d’acquisition intégrée pour spectroscope de RMN portable par Duc-Vinh Nguyen, Guilherme Baumgarten, Lucas Werling, Norbert Dumas, Morgan Madec, Latifa Fakri-Bouchet, José Bernardo, Wilfried Uhring, Luc Hebrard and Joris Pascal. (Paper ID:9925)
• Un convertisseur numérique-analogique pour l’agrégation de porteuses 5G par Pierre Ferrer, François Rivet, Hervé Lapuyade and Yann Deval. (Paper ID:9968)
• A new figure of merit for neural network efficiency par Hugo Waltsburger, Erwan Libessart, Chengfang Ren, Anthony Kolar and Régis Guinvarch. (Paper ID:8066)
• Optimisation de l’efficacité énergétique pour l’IA embarquée par Zhuoer Li and Sébastien Bilavarn. (Paper ID:8621)
• FPGA implementation of 2D Convolution using OneAPI and OpenCL par Daouda Diakite and Nicolas Gac. (Paper ID:8630)
• Accélération, sur FPGA, de l’apprentissage profond basé sur les transformers par Fayçal Baaddouch, Patrick Schweitzer and Serge Weber. (Paper ID:8686)
• Un outil pour l’aide à la conception d’ASICs numériques par Philippe Benabes. (Paper ID:4200)
• An Analytical Model for Hybrid Network on Chip Latency Analysis par Ibrahim Krayem, Cedric Killian and Daniel Chillet. (Paper ID:9291)
• A Wideband Power Amplifier for Sub-6 GHz 5G Applications Using Second Harmonic Processing Techniques in 28nm FDSOI Technology par Remi Queheille, Nathalie Deltimple, François Rivet, Yann Deval and Eric Kerhervé. (Paper ID:159)
• Assessment of the impact of static field inhomogeneity on the performance of miniaturized NMR devices par Guilherme Baumgarten, Morgan Madec, Duc-Vinh Nguyen, Lucas Werling, Joris Pascal, Chunchesh Malangi Gajendramurthy, Philippe Bertani, Jean-Pierre Djukic and Luc Hébrard. (Paper ID:6720)

Responsables de la session : TBD

Horaire et date de la session : Mardi 27/06 de 15h à 16h

Posters présentés :

• Work-in-progress: Ontology-driven Generation of AADL architecture Models par Perig Dissaux, Frank Singhoff and Catherine Dezan. (Paper ID:2191)
• High speed electronical and optical communication at cryogenic temperature for quantum computers par Florian Cailliau, Yvail Thonnart and José Luis Gonzalez Jimenez. (Paper ID:961)
• Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors par Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O’Connor, Oskar Baumgartner and David Pirker. (Paper ID:4308)
• Stochastic multiply-accumulate in photonics with phase-change materials par Raphael Cardoso, Clément Zrounba, Mohab Abdalla, Fabio Pavanello, Ian O’Connor and Sebastien Le Beux. (Paper ID:6140)
• A design space exploration approach to jointly optimize security and schedulability in TSP systems par Ill-Ham Atchadam, Frank Singhoff, Hai Nam Tran and Laurent Lemarchand. (Paper ID:2048)
• Random Number Generation using NCVO par Ali Rida Ismail, Slavisa Jovanovic, Sébastien Petit Watelot and Hassan Rabah. (Paper ID:5196)
• Estimation du coût d’inférence des réseaux de neurones convolutifs dans un microcontrôleur par Thomas Garbay, Petr Dobias, Wilfried Dron, Pedro Lusich, Imane Khalis, Andrea Pinna and Bertrand Granado. (Paper ID:703)
• Implementation of a Pre-Processing Chain of Radar-Based Human Activity Recognition par Alexandre Bordat, Petr Dobias, Julien Le Kernec, David Guyard and Olivier Romain. (Paper ID:1447)
• Conception d’architectures de FFT pour FPGA à base de modèles comportementaux par Hugues Almorin, Bertrand Le Gal, Jeremie Crenne, Christophe Jego and Vincent Kissel. (Paper ID:1452)
• Optimal Trace Synthesis for Scheduling Intermittent Embedded Systems par Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou and Olivier Roux. (Paper ID:3447)
• IoT-Blockchain Based Ecosystem using Hyperledger Sawtooth par Luc Gerrits, Cyril Naves Samuel and Francois Verdier. (Paper ID:914)
• Alimentation par énergie RF d’une Wake-Up Radio ultra faible consommation par Jesus Argote Aguilar, Florin Hutu, Guillaume Villemaud, Matthieu Gautier and Olivier Berder. (Paper ID:4730)
• Micro-device for the characterization of biological cells exposed to electric fields using impedance spectroscopy par Rémi Bettenfeld, Julien Claudel and Djilali Kourtiche. (Paper ID:720)
• Antidictionary-Based Cardiac Arrhythmia Classification par Julien Duforest, Benoît Larras, Deepu John, Olev Märtens and Antoine Frappé. (Paper ID:1004)
• Configuring a Universal BIST Solution for CMOS Image Sensors par Julia Lefevre, Philippe Debaud, Arnaud Virazel and Patrick Girard. (Paper ID:2543)
• A low-cost high throughput microfluidics system for multi-thousands droplets per second sorting based on time resolved fluorescence measurement par Wassim Khaddour, Norbert Dumas, Foudil Dadouche, Morgan Madec and Wilfried Uhring. (Paper ID:3999)
• A 3.2 Gbps Clock Recovery Circuit based on Phase-Locked-Loop with Injection-Locked Ring Oscillator par Dorian Vert, Michel Pignol, Vincent Lebre, Emmanuel Moutaye, Florence Malou and Jean-Baptiste Begueret. (Paper ID:6634)
• Addressing Wireless Connectivity in Infrasound Measurement Systems with Data Resolution Optimisation par Samir-Sharif El Rhaz, Antoine Courtay, Anthony Hue, Titouan Hamon and Olivier Berder. (Paper ID:7354)
• Une PLL à Double boucle basée sur une architecture N-entière pour une faible résolution de fréquence en technologie 28nm CMOS FD-SOI par Mateus Bernardino Moreira, François Sandrez, Md. Sazzad Hossain, Hervé Lapuyade, François Rivet and Yann Deval. (Paper ID:7873)
• Distributed Artificial Intelligence Integrated Circuits For Ultra-Low-Power Smart Sensors par Mathieu Chêne, Benoit Larras and Antoine Frappé. (Paper ID:212)
• Deep Neural Network Feasibility Using Analog Spiking Neurons par Thomas Soupizet, Zalfa Jouni, Joao Frischenbruder Sulzbach, Aziz Benlarbi-Delai and Pietro Maris Ferreira. (Paper ID:6680)
• Digital Oscillatory Neural Networks for AI Edge Applications par Madeleine Abernot, Corentin Delacour, Gabriele Boschetto, Stefania Carapezzi, Thierry Gil, Nadine Azemard and Aida Todri-Sanial. (Paper ID:7683)
• Studying the Behavior of Stochastic Spintronic Spiking Neuron par Sara Mannaa and Elena-Ioana Vatajelu. (Paper ID:9109)
• Input-Aware Approximate Computing par Ali Piri, Mario Barbareschi, Bastien Deveautour, Ian O’Connor, Marcello Traiola and Alberto Bosio. (Paper ID:1084)
• Modeling and Analysis of Cache-Coherent Chip-to-Chip Interconnect par Luis Bertran Alvarez, Alejandro Nocua, Pascal Benoit and David Novo. (Paper ID:1762)
• On Using Cell-Aware Models for Testing SRAM Memories par Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, Gregory Di Pendina, Patrick Girard and Arnaud Virazel. (Paper ID:4759)
• Novel method for modeling the local electro-thermal behavior of discrete power diode using Verilog-A in a standard CAD environment par Achraf Kaid, Jean-Baptiste Kammerer, Fabrice Roqueta and Luc Hébrard. (Paper ID:5308)