Guide to Computer Processor Architecture: A RISC-V Approach, with High-Level Synthesis

Calcul embarqué haute performance, Technologies du futur, Méthodes et outils

A new book on processor architecture will be published by Springer in december 2022 (written by Bernard Goossens).

https://link.springer.com/book/9783031180248

The book  presents a succession of RISC-V processor implementations in increasing difficulty (non pipelined, pipelined, deeply pipelined, multithreaded, multicore). Each implementation is shown as an HLS code in C++ which can really be synthesized and tested on an FPGA based development board. A github provides all the resources to build the processor IPs described in the book.

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