The development of advanced technologies is changing the way RF circuits are designed. In the 90s, the growing interest for telecommunications and GSM pushed designers to use CMOS technologies in order to reduce fabrication costs which were an issue to address mass markets. At this time, the low FT of available technologies has pushed designers to work in high inversion in order to meet the requirements in terms of bandwidth. Many design methods have emerged based on the small signal model of the transistor in strong inversion region of operation.
Today, the paradigm is changing. Advanced technologies have very high FT and the demand for low power systems is very high. The issue of mobility or Internet of Things appeal for a break in the consumption of RF circuits. The use of the MOS in strong inversion is no longer necessary and the trend is moving towards polarization in low or moderate inversion regime. Indeed, the efficiency of the component in terms of energy, characterized by the inversion coefficient or the gm / Id ratio, increases when the channel inversion decreases.
In addition, the analytical models of the MOS based on the different operating regions are no more useful for designer when advanced technologies are considered. This leads to an intensive use of tuning operations in RFIC design which reduces the link between technology and design.
The aim of this IEEE – SoC2 joint day is to present new RF design technics dedicated to low power applications. Morning keynotes will focus on inversion coefficient based design technics for RF low power. Afternoon presentation will be extended to other low power design technics in order to have a larger scope on recent advances in RF low power application.
Télécharger le PDF