Le GdR SOC2 adresse, entre autres, les problématiques des méthodes et outils de conception des systèmes sur puce au sens large, incluant électroniques analogique et numérique et architectures matérielles. Dans ce cadre, une série de webinaires courts voués à donner différents éclairages sur le thème “Outils de Conception” est prévue. Ces webinaires auront une durée approximative de 1h30 pour 2 exposés suivis d’une séance de questions.

Le premier webinaire sur les outils pour la synthèse de haut-niveau est prévu le 08/04/2021 de 14h à 15h30, et proposera les deux exposés ci-dessous :

Exposé 1 : On Intermediate Representations for High(er)-Level Synthesis

  • Speaker: Christophe Alias, LIP, Inria
  • Abstract: With the emergence of reconfigurable FPGA circuits as a credible alternative to GPUs for HPC acceleration, new compilation paradigms are required to map high-level algorithmic descriptions to a circuit configuration (High-Level Synthesis, HLS). In particular, novel parallelization algorithms and intermediate representations (IR) are required, and still not used on today’s HLS tools. In this talk, we present the data-aware process networks (DPN), a dataflow intermediate representation suitable for HLS in the context of high-performance computing. DPN combines the benefits of a low-level dataflow representation – close to the final circuit – and affine iteration space tiling to explore the parallelization trade-offs (local memory size, communication volume, parallelization degree). We outline our compilation algorithms to map a C program to a DPN (front-end), then to map a DPN to an FPGA configuration (back-end). Finally, we present synthesis results on compute-intensive kernels from the Polybench suite.

Exposé 2 : Toward Speculative Loop Pipelining for High-Level Synthesis

  • Speaker: Steven Derrien, IRISA, Université de Rennes 1
  • Abstract: Loop pipelining (LP) is a key optimization in modern high-level synthesis (HLS) tools for synthesizing efficient hardware datapaths. Existing techniques for automatic LP are limited by static analysis that cannot precisely analyze loops with data-dependent control flow and/or memory accesses. We propose a technique for speculative LP that handles both control-flow and memory speculations in a unified manner. Our approach is entirely expressed at the source level, allowing a seamless integration to development flows using HLS. Our evaluation shows significant improvement in throughput over standard loop pipelining techniques.

Inscription

Lien pour l’inscription : https://evento.renater.fr/survey/inscription-journee-thematique-hls-gdr-soc2-1efbyfi4

Cette inscription nous permettra de vous contacter en cas de problème technique.

Visioconférence

Lien zoom : https://zoom.us/j/96433039667?pwd=cDNDdzBrb1FZc0RKbEdNN3lCa1Aydz09

Meeting ID: 964 3303 9667
Passcode: 193231