Présentation

Suite au barcamp « La NVM dans tous ces états ! » organisé à Fréjus les 26 et 27 mars 2018, le GDR SOC2 organise une nouvelle journée autour des technologies émergentes dans le domaine des mémoires non volatiles (ENVM). Cette journée portera plus particulièrement sur les aspects logiciels des systèmes informatiques (embarqués ou non) intégrant ces technologies.

Elle s’articule autour de 6 exposés qui couvrent les thèmes suivants :

  • Les technologies (E)NVM et les défis liés à leur intégration dans les systèmes informatiques.
  • Les opportunités offertes en terme de consommation énergétique et les techniques de compilation permettant de créer des programmes efficaces.
  • Le calcul intermittent, un paradigme pour les systèmes embarqués sans batterie, et le support de ce paradigme au sein des compilateurs et des systèmes d’exploitation.

La journée se déroulera le 9 septembre 2019 à Nantes, Campus Chantrerie, Polytech’Nantes, bâtiment IHT, salle A101 (plan d’accès ici). Pour des raisons logistiques, l’inscription est gratuite mais obligatoire via ce formulaire avant le 26 août 2019.

Programme

9h15Accueil
10hMémoires non-volatiles émergées et émergentes, intégration dans les systèmes informatiquesJalil Boukhobza
10h50Silent Store Analysis and Elimination for Improving NVM Energy-EfficiencyAbdoulaye Gamatié
11h40Compiler Optimizations in the presence of non-volatile memoriesErven Rohou
12h30Déjeuner
14hDynamic Heterogeneous Memory Allocation for embedded devicesTristan Delizy
14h50Worst-Case Energy Consumption Aware Compile-Time Checkpoint Placement for Energy Harvesting SystemsBahram Yarahmadi
15h40Ensuring Peripheral Consistency on Intermittent Systems with NVRAMGautier Berthou

Résumé des exposés

Jalil Boukhobza, Lab-STICC : Mémoires non-volatiles émergées et émergentes, intégration dans les systèmes informatiques

4 Zettaoctets de données générées en 2013, 44 à l’horizon 2020 et 185 en 2025. Ces chiffres donnent le vertige. Ils illustrent parfaitement cette nouvelle ère du déluge de données, devenues un enjeu économique et sociétal majeur et dont le traitement se fait à la vitesse du maillon le plus faible dans un système informatique : le système de stockage. Il est donc crucial d’optimiser le fonctionnement de ce dernier. Lors de la dernière décennie, ces systèmes ont connu une révolution majeure, l’avènement des mémoires flash, et d’autres bouleversements sont à venir. Dans cette présentation, je vais tenter de donner un aperçu des technologies de mémoires non-volatiles émergées (mémoire flash principalement) et émergentes (PCM, ReRAM, MRAM …). Je vais aussi essayer d’introduire quelques défis liés à leur intégration dans les systèmes informatiques.

Abdoulaye Gamatié, LIRMM : Silent Store Analysis and Elimination for Improving NVM Energy-Efficiency

A Store instruction is said “silent” if it writes in memory a value that is already there. The ability to detect silent stores is important, because they might indicate performance bugs, might enable code optimizations, etc. Silent stores are traditionally detected via profiling tools. But, what about the following question: is it possible to predict silentness by analyzing the syntax of programs? The process of building an answer to this question is interesting in itself, given the stochastic nature of silent stores, which depend on data and coding style. This talk deals about silent store analysis and elimination with the aim of optimizing programs running on emerging non-volatile memory systems, where memory writes are costly in latency and energy.

Erven Rohou, INRIA : Compiler Optimizations in the presence of non-volatile memories

Energy-efficiency has become one major challenge in both embedded and high-performance computing domains. Different approaches have been investigated to solve the challenge, e.g., system runtime management, heterogeneous multicores and device-level power management. Non-volatile memories (NVMs) have emerged as a way to reduce the consumption of the memory subsystem. In this talk, we will present two compiler optimizations recently developed at the Inria/PACAP group to take into account characteristics of NVMs: the read/write asymmetry fo memory accesses, and variable retention times.

Tristan Delizy, CITI : Dynamic Heterogeneous Memory Allocation for embedded devices

Reducing energy consumption is a key challenge to the realisation of the Internet of Things. While emerging memory technologies may offer power reduction, they come with major drawbacks such as high latency or limited endurance. As a result, system designers tend to juxtapose several memory technologies on the same chip. We aim to provide embedded application programmer with a transparent software mechanism to leverage this memory heterogeneity. This work studies the interaction between dynamic memory allocation and memory heterogeneity. We provide cycle accurate simulation of embedded platforms with various memory technologies and we show that different dynamic allocation strategies have a major impact on performance. We demonstrates that interesting performance gains can be achieved even for a low fraction of heap objects in fast memory, but only with a clever placement strategy between memory banks. We evaluate an efficient strategy based on application profiling in our simulator.

Bahram Yarahmadi, INRIA : Worst-Case Energy Consumption Aware Compile-Time Checkpoint Placement for Energy Harvesting Systems

A large and increasing number of Internet-of-Things devices are not equipped with batteries and harvest energy from their environment. Many of them cannot be physically accessed once they are deployed (embedded in civil engineering structures, sent in the atmosphere or deep in the oceans). When they run out of energy, they stop executing and wait until the energy level reaches a threshold. Programming such devices is challenging in terms of ensuring memory consistency and guaranteeing forward progress. Previous work has proposed to insert checkpoints in the program so that execution can resume from well-defined locations. We propose to define these checkpoint locations based on worst-case energy consumption of code sections, with limited additional effort for programmers. As our method is based upon worst-case energy consumption, we can guarantee memory consistency and forward progress.

Gautier Berthou, CITI : Ensuring Peripheral Consistency on Intermittent Systems with NVRAM

À venir.

Contacts

Pour toute question, n’hésitez pas à contacter les organisateur de cette journée qui sont Abdoumlaye Gamatié (abdoulaye.gamatie-at-lirmm.fr), Maria Méndez Real (maria.mendez@univ-nantes.fr) et Sébastien Faucou (sebastien.faucou@ls2n.fr).