RISC-V Week – Paris – Octobre 2019
Join us for the “Semaine RISC-V” (RISC-V Week) in Paris, 1st-3rd October!
The maturity level of RISC-V, a free and open RISC instruction set architecture (ISA), is raising up quickly, supported by numerous industrial offering, active academic research and several initiatives supporting the emerging open hardware ecosystem.
At the “Semaine RISC-V” you will enjoy tutorials, keynotes, series of short to-the-point presentations on advanced topics, and in-depth presentations on RISC-V-based solutions. You will get up-to-date results on RISC-V R&D, its impact on systems-on-a chip (SoC), critical embedded system or cyber-physical system (CPS) design, and details on legal and strategic issues related to open source HW IP management.
You will also discover recent results of research activities on software, hardware and system design that provide trends for future industrial solutions:
• Micro-architecture research
• RISC-V cores
• RISC-V and low power designs
• RISC-V ISA extensions
• Compilation and languages
• Security & safety
• Open source HW
• Open source design flow and verification
The three day conference will be in Paris downtown. It will be a great opportunity to discuss new collaboration across industrial, academic and support organizations involved in this emerging and challenging ecosystem.
You will find more information at: https://open-src-soc.org.