Sécurité et intégrité des systèmes


This thesis will focus on the hardware/software co-design of
countermeasures against physical attacks, in particular, fault injection
attacks. We will aim at developing new securing solutions that can be
applied to all software components whatever their algorithmic nature
(e.g. contrary to cryptography-specific countermeasures); the
countermeasures will be able to exploit hardware security properties
available on the target architecture. To do so, we will modify the
processor micro-architecture, and exploit code transformation and
optimization strategies of the compiler to design new countermeasures
with a high security level and a low performance overhead. The thesis is
supported by the ANR project COFFI, starting February 2019 (duration 42


This thesis will focus on the security of embedded systems, and to a
certain extent to the security of all computing systems. In particular,
we focus on so-called *physical attacks*, which are typically separated
in two classes: side-channel attacks, which are observation-based, and
fault injection attacks, which exploit the effects (or the lack of
effect) of a physical perturbation on the targeted chip. Physical
attacks exploit a partial knowledge of the target attacked to break the
standard security assumptions provided by traditional cryptanalysis. For
example, the symmetric block cipher AES, which is considered secure by
the traditional cryptanalysis, is highly vulnerable in presence of
side-channel or fault injection attacks.

In this thesis, we will focus on the hardware/software co-design of
countermeasures against physical attacks, in particular, fault injection

Securing a full system against physical attacks relies on the use of
many hardware and software countermeasures. In a secured product, such
as a Smart Card product, the components the most vulnerable to physical
attacks, such as the cryptographic primitives, are usually implemented
in specific components, secured by the use of many *ad hoc* protections
both at the hardware and software levels. Hardware implementations can
offer better performance and a smaller attack surface, and as a
consequence a secured product will embed hardware implementations of the
most critical components of specific features such as a cryptographic
primitive. However, a whole embedded secured system also needs software
security mechanisms because many components, outside of cryptographic
components, may also need dedicated protections mechanisms that cannot
be implemented only in hardware. For example, the bootloader, which is a
key element in the security of an embedded system.

Superimposition of hardware and software protections. The scientific
literature already presents many ways to secure a system at the hardware
or at the software levels. In practice, a product is secured by the
superimposition of many hardware and software countermeasures. Such
countermeasures are usually blind to each other, and hence cannot
usually benefit from the knowledge of the presence of other
countermeasures, in order, e.g., to improve the global security level of
the system, or to reduce the performance overhead resulting incurred by
countermeasures. The co-design of countermeasures both in hardware and
software was mostly used in approaches for Control-Flow Integrity (CFI),
and recently for execution integrity of all the machine instructions of
a program \[1, 4\]. Also of interest is for example the confidentiality
of programs \[1, 2\]. To the best of our knowledge, all these works
start with a new hardware design, and the software toolchain (in
particular the compiler) is afterwards adapted to take into account the
hardware particularities. In this thesis, we aim at taking the opposite
approach: start from the many opportunities for program transformations
offered by a compiler to design innovative security mechanisms, and
ground those mechanisms on hardware adaptations to offer a high level of

The starting point of the thesis will be based on:

– The results of the thesis of Thierno Barry (2014-2017), which
provided an initial framework for the compilation of
counter-measures against fault injection attacks.

– A patent on a security mechanism with hardware-software co-design,
against fault injection attacks. The countermeasure described in the
patent could constitute a starting point for some experimental
research work.

– Research experiments will be based on the RISC-V architecture. The
DACLE/LIALP laboratory has already a strong experience on a full
prototyping environment for the simulation of RISC-V architectures
and programs.


The position is 3-year long, starting during the second semester of
2019. The PhD candidate will be hosted at CEA Grenoble, France. The PhD
student will be co-supervised by Damien Couroussé, CEA, and by Karine
Heydemann, LIP6 (directrice de recherches).

The project COFFI (ANR 2018, starting February 2019, for 42 months) is
partially funding this PhD position. The project focuses on the
co-design of countermeasures against physical attacks, and this thesis
will constitute one of the core contributions to the project. The
project consortium is composed of: SAS laboratory (joint team Mines de
Saint-Étienne / CEA), Sorbonne Université (LIP6), INVIA, and CEA-DACLE
at Grenoble. The student will have the opportunity to play an active
role in this project.

The CEA (Alternative Energies and Atomic Energy Commission) is the
leading French research institution: it was recently recognized as The
World’s Most Innovative Research Institution by Reuters (Top 25 Global
Innovators – Government list). Its Technological Research Division,
located in Grenoble and near Paris, is specialized in Information
Technology and Renewable Energies. The student will be part of a
multi-disciplinary team with experts in embedded software,
cyber-security for the Internet-of-Things, hardware design, and machine


Candidates should have a Master degree in Computer Science. They should
be familiar with at least one of the following topics: compilation,
computer architecture, cyber-security.

Selected bibliographic references

1. M. Werner, T. Unterluggauer, D. Schaffenrath, and S. Mangard,
‘Sponge-Based Control-Flow Protection for IoT Devices’,
arXiv:1802.06691, 2018.

2. T. Hiscock, O. Savry, and L. Goubin, ‘Lightweight Software
Encryption for Embedded Processors’, DSD, 2017.

3. N. Timmers and A. Spruyt, ‘Bypassing Secure Boot using Fault
Injection’, Black Hat Europe 2016.

4. R. de Clercq et al., ‘SOFIA: Software and control flow integrity
architecture’, DATE, 2016.


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